DATE
23-25 July 2020
In this talk, I will discuss new, open, semiconductor business models and paradigms that can accelerate start ups reach mature products by a factor of 2. This approach takes ...a customer centric and employs rapid ideation and chip design starts to enable to chip to system innovation for edge computing. I will examine several case examples where this model is seeing global success.
Dr. Sherwani brings over 25 years of experience in entrepreneurship, technical engineering and general management. Dr. Sherwani has founded and co-founded nine companies ...in systems, software, and services. His recent focus has been on enterprise software, data analytics, and blockchain technologies. Prior to Peernova, Dr. Sherwani co-founded Open-Silicon, a leading provider of ASIC and system solutions. As the founder and General Manager of Intel Microelectronics Services, he pioneered Open methodology for EDA. He also founded Brite Semi, a leading solution provider in China/APAC. He has served on the boards of various companies, including Touchstone Inc., and Integration Associates. Dr. Sherwani is a noted author having written several books and over 100 articles on various aspects of algorithms, parallel computing, and EDA. In particular, he wrote the leading textbook on algorithms for chip-design automation, which is currently used in universities worldwide. Dr. Sherwani served as a Professor at Western Michigan University, where his research focused on algorithms, EDA, Combinatorics, and parallel computing. He received his Ph.D from the University of Nebraska-Lincoln.
In this talk, we will start off with the RF design fundamentals. We will review key concepts required for RF IC design. A high-level overview of the transceiver ...architecture along with a closer look at the RF building blocks will provide you with deeper insights. We will review current RF CMOS technology trends. Challenges faced in the integration of RF IP in digital SOCs will be discussed. In the end, we will look under the hood of a few published RF SOCs to understand trends in Wi-Fi, 5G, and 60 GHz applications.
Professor Rajesh Zele (website) is the alumnus of IIT Bombay (B.Tech. 1989). He joined IIT Bombay as a Professor in the Electrical Engineering Department after 22 ...years of industry experience. Before joining IIT, Prof. Rajesh Zele was the Director at MaxLinear, developing the next generation CMOS RF and Mixed-Signal SOCs for Digital Cable and Satellite Communications. Prof. Rajesh Zele has also served as the Vice President of MindTree, leading the team for Bluetooth and short-range wireless transceivers. He founded the start-up Alereon Semiconductors in Pune to develop ultra-wideband RFICs for Wireless USB products. Before Alereon, he was the Director of Engineering at Zilker labs developing power management products. He established the Austin Design Center for the start-up FET and managed the technical team responsible for 10Gbps optical networking products. Prof. Rajesh Zele has an extensive background in wireless transceivers at Motorola, where he was an IC design manager for the Talk-About radio platform. He has presented talks at various IEEE conferences and symposiums. He has written over 20 papers, co-authored a book chapter, and holds 8 US patents. Prof. Rajesh Zele has received Ph.D. in ECE from Carnegie Mellon University, MSEE from Oregon State University, and is also a Senior Member of IEEE.
Prof. Zele recently served as the Professor-In-Charge for IIT Bombay Research Park where industry members are invited to start their R & D operations on the IIT Bombay campus to promote Industry-Academia collaboration. He is currently serving as a board member for SINE, IIT Bombay’s start-up initiative.
As the computational demands on notebooks and cellphones have rapidly increased over the past decade, mobile electronic systems have adopted extensive power management strategies ...to ensure battery life. These include aggressive voltage-frequency scaling, with the circuit operating at very low energy saving voltages when computational loads are minimal. Unfortunately, the impact of manufacturing process variations on circuit timing is greatly amplified during low voltage operation, causing some circuits to experience timing failure in low power modes. Ideally, such “defective†ICs, containing unacceptably slow outlier transistors from random statistical parameter variations, should be detected and screened out by post manufacturing tests. However, widely used scan timing tests are unable to reliably detect such failures, increasingly forcing industry to adopt expensive system level functional tests as a final test screen. We analyze this paradigm shift in IC testing and its implications.
Adit Deva Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, where he has served on the faculty since 1991. Earlier he has held faculty ... positions at the University of Massachusetts in Amherst, and Virginia Tech, in Blacksburg. He has also held visiting professorships at the University of Freiburg, Germany, and the University of Tokyo, Japan, and a
Ruchir has over 20 years of experience in the semiconductor industry focused having executed at multiple levels of responsibilities in design and development of ASIC, FPGA and ... PCB products. In all these years, Ruchir has either directly worked on or worked with customers on over 200 IC Tapeouts.
After spending close to 10 years in the IC development roles, Ruchir moved into EDA and Applications. In this role Ruchir has held various leadership roles. In these roles, Ruchir has worked with many customers world-wide and helped them to define the problem and then work to create solutions. Ruchir spent 11 years in Mentor, US and then moved to India in 2005 to start building the application engineering team in India.
Until recently, Ruchir was leading a global team on DFT and Analog/Mixed Signal technologies. Now, Ruchir leads the India technical organization that works with customers across all product lines of Mentor.
Ruchir graduated from Wayne State University, Michigan with a Masters in Computer Engineering and has an undergraduate degree in Electronics & Instrumentation from Indore University, India.
Dora Smith is the senior director of the global academic program for Siemens Digital Industries Software. Under Dora’s leadership, the global academic program is a strategic ... initiative for the company. The program empowers the next generation of digital talent through project-based learning, STEM competitions and industrial strength software and curriculum to support more than 1 million students and more than 3,000 institutions worldwide.
Dora serves in academic-industry advisory roles such as director on the American Society for Engineering Education’s Corporate Member Council. Dora is an accredited business communicator with more than 20 years of experience. She has spent her career in the engineering and manufacturing industry with leadership roles across disciplines. Previously, she held executive management positions at CAD Potential (now Tata Technologies), where she developed the company’s first academic and certification programs. Prior to that, she directed the Unigraphics Users Group (now PLM World) an independent, not-for-profit organization supporting the engineering community. She also served as president on the board of directors of IABC St. Louis. Dora earned her bachelor’s degree in journalism from the University of Missouri-Columbia and a master’s degree in business administration from Washington University.
Siemens Digital Industries Software is driving transformation to enable a digital enterprise where engineering, manufacturing and electronics design meet tomorrow. Our solutions help companies of all sizes create and leverage digital twins that provide organizations with new insights, opportunities and levels of automation to drive innovation. For more information on Siemens Digital Industries Software products and services, visit sw.siemens.com or follow us on LinkedIn, Twitter, Facebook and Instagram. Siemens Digital Industries Software – Where today meets tomorrow.
The IEEE 1687 standard is rapidly gaining popularity in the industry and becoming the de facto method to deal with Macro Tests and IP handoff and integration. IP developers can use... the ICL and PDL files to describe their Instruments/IP blocks with their functional test patterns, and these same files can be used by an EDA tool to re-target the functional tests to the SoC boundary in an automated and plug and play manner. In this talk we discuss what is the problem for which the standard was evolved and how we can leverage IEEE 1687 for access, control and configuration of the test structures embedded within an IP block. We will cover some of the basics as well as advanced topics including how SIBs can be used as a building block to describe the 1687 compliant test access architecture. Some of the practical applications of the technology are also touched upon.
Rajesh is currently working as Director R&D at Cadence Design System, Noida, and leads a team working on IEEE 1687 & Low Power Tests. Prior to joining Cadence, he was Engineering ... Manager at Synopsis Bangalore office. He has over 24 years of experience spanning across multiple domains & technologies. His current interests are in Low Power Test methodologies and Embedded Macro Tests using IEEE 1687 and 1500. His contribution in the field of research includes five US patents and multiple publications at ITC (both India & US), ATS, NATW etc. He has master’s in management and bachelor’s in electrical engineering from DEI, Dayalbagh Agra.