Program

Tutorials

23rd July 2020 will be a tutorial day for VDAT2020.

Tutorial 1

Topic: System Design Flow on Zynq using Vivado High-Level Synthesis
Date & Time: 23-July-2020 10.00 - 13.00

Tutorial 2

Topic: Secure SHAKTI
Date & Time: 23-July-2020 10.00 - 13.00

Abstract of the Tutorial: The course provides professors, students, Research Scholars and working professionals with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS.

Outline of the Tutorial: Introduction to HLS Using Vivado HLS. Lab1: Creating Project and Understanding Reports Experience a basic design flow of Vivado HLS and review generated Output. Improving Performance: Lab2: Optimizing Performance through Pipelining Use pipelining technique to improve performance. Creating an Accelerator: Lab 3: Creating a Processor System using Accelerator Profile an application performing a function both in software and hardware. Create an accelerator in Vivado HLS. Use the generated accelerator to build a complete system.

Speaker: Prakash G, CoreEL Technologies (I) Pvt. Ltd.

E-mail: prakash.g@coreel.com

Abstract of the Tutorial:With the advent of IoT and Ubiquitous computing, millions of embedded devices would be connected and accessible over the Internet. Unfortunately, most of these embeddedd devices are not designed to handle the wide range of security threats ranging fromTrojans, Backdoors, and Malware to Physical and Side-Channel attacks. Contemporary protection mechanisms partially protect against these attacks with considerable overheads in size, power requirements, and costs. Developing secure embedded devices would require a clean slate approach with security as a fundamental design parameter.

Outline of the Tutorial: In this tutorial we look at some of our efforts at IIT Madras to develop a secure microprocessor, which would form the heart of an embedded device. We build on the our homebred, open-source, Linux bootable, RISC V processor, SHAKTI, to add features that would harden the processor for security. This tutorial will mainly focus on threea aspects First, we would look at the problem of buffer overflows, one of the most exploited vulnerabilities affecting a large number of commercial software. Next, we discuss the problem of side-channel attacks, which are capable of breaking strong ciphers like AES and RSA within a few minutes. Finally, we discuss how microprocessors can be protected against Hardware Trojans and Backdoors that may be introduced by third party fabrication units.

Speaker: Prof. V. Kamakoti, Department of Computer Science & Engineering, IIT Madras

Tutorial 3

Topic: Analog VLSI Circuit Design
Date & Time: 23-July-2020 14.30 - 17.30

Tutorial 4

Topic: VLSI Testing
Date & Time: 23-July-2020 14.30 - 17.30

Abstract of the Tutorial: Phase-locked loop (PLL) is a key building block in processing units, wireline and wireless systems. PLL plays an important role in clock generation and distribution in the processing units, clock generation and clock-and-data recovery in the wireline systems, frequency synthesis for transceivers in the wireless systems, etc. For decades there have been many advances in PLL architectures and circuit techniques considering performance, power and cost. This tutorial gives some insight into PLL design basics for circuit designers, and an overview of fractional frequency synthesis.

Speaker: Dr. Debashis Mandal, Department of Electrical Engineering, Indian Institute of Technology Kharagpur.

Outline of the tutorial: Basics of PLL, loop stability, PLL noise, PLL building blocks, different architectures of PLL, basics of fractional frequency synthesis.

E-Mail: debashis@ee.iitkgp.ac.in

Abstract of the Tutorial: This tutorial provides professors, students, research scholars and industry professionals a sneak peek into the world of VLSI testing.

Outline of the tutorial: Need for VLSI testing, DFT techniques for various SoC components, overview of defects, faults and fault models, types of testing, basic scan design and scan design rules, overview of scan compression and logic BIST, fundamentals of DFT standards (IEEE11491.x, IEEE1500, IEEE1687), basics of memory testing.

Speaker: Abhishek Chaudhary, Rambus Chip Technologies India Pvt. Ltd.

E-Mail: achaudhary@rambus.com



Main Conference Program

DATE

23-25 July 2020

location

IIT Bhubaneswar, Argul

Call For Papers

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Speakers

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